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NASA is testing a new radiation-hardened system-on-a-chip designed to boost spacecraft computing power by 500 times, enabling autonomous decision-making and faster data analysis for deep space missions.

Delivering roughly 500 times the performance of current spaceflight processors, NASA’s latest radiation-hardened chip aims to revolutionize onboard computing for future missions. This advanced system-on-a-chip (SoC) is engineered to operate reliably under extreme space conditions while supporting artificial intelligence capabilities.
The High Performance Spaceflight Computing initiative at NASA is focused on enhancing spacecraft computing to meet the demands of upcoming exploration missions. Traditional space processors prioritize durability but lack the speed and flexibility needed for autonomous operations and rapid data processing.
NASA envisions spacecraft equipped with this new chip to independently analyze data and respond to unforeseen events without waiting for commands from Earth. Such autonomy is critical given the communication delays inherent in deep space exploration.
“Building on the legacy of previous space processors, this new multicore system is fault-tolerant, flexible, and extremely high-performing,” stated Eugene Schwanbeck, program element manager at NASA’s Langley Research Center. “NASA’s commitment to advancing spaceflight computing is a triumph of technical achievement and collaboration.”
Beyond autonomy, the chip’s enhanced processing power will accelerate scientific discoveries by enabling faster onboard analysis of large data sets, which is essential for missions to the Moon, Mars, and beyond.
Engineers at NASA’s Jet Propulsion Laboratory (JPL) have subjected the processor to a battery of tests simulating the harsh realities of space, including radiation exposure, thermal extremes, and mechanical shocks. These assessments ensure the chip can endure the intense radiation and temperature fluctuations encountered during missions.
“We are putting these new chips through the wringer by carrying out radiation, thermal, and shock tests while also evaluating their performance through a rigorous functional test campaign,” explained Jim Butler, project manager at JPL.
Testing also includes simulations of landing scenarios from actual NASA missions, which demand processing large volumes of sensor data in real time. This approach helps verify the chip’s capability to handle power-intensive tasks critical for safe planetary landings.
Initial testing began in February and will continue for several months. Early results indicate the processor meets performance expectations and maintains resilience under simulated space conditions. The team commemorated the start of testing with an email titled “Hello Universe,” echoing the historic tradition of early computer communications.
The chip’s development is a joint effort between JPL and Microchip Technology Inc., a semiconductor company based in Arizona. Early prototypes have been shared with partners in defense and commercial aerospace sectors to explore broader applications.
This technology is expected to empower spacecraft with real-time artificial intelligence, enabling them to adapt to unexpected challenges without human intervention. It will also facilitate the rapid processing, storage, and transmission of vast scientific datasets collected during deep space missions.
Designed as a compact system-on-a-chip, the device integrates multiple computing components into a single unit small enough to fit in a hand. While SoCs are common in consumer electronics like smartphones, this version is engineered for long-term operation millions of miles from Earth, enduring conditions far beyond typical commercial devices.
Once certified for spaceflight, NASA plans to deploy the chip across a variety of platforms, including Earth orbiters, planetary rovers, crewed habitats, and deep space probes. Microchip also intends to adapt the technology for terrestrial industries such as aviation and automotive manufacturing.
The Space Technology Mission Directorate’s Game Changing Development program at NASA Langley oversees this project, guiding it from initial concept through development and testing. Managed by Caltech, JPL selected Microchip as a partner in 2022, with the company investing in its own research and development to advance the processor.